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CHO: Towards a Benchmark Suite for OpenCL FPGA Accelerators

Geoffrey Ndu, Javier Navaridas, Mikel Lujan

In: 3rd IWOCL International Workshop on OpenCL ; 11 May 2015-13 May 2015; Palo Alto, California, USA. 2015.

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Abstract

Programming FPGAs with OpenCL-based high-level synthesis frameworks is gaining attention with a number of commercial and research frameworks announced. However, there are no benchmarks for evaluating these frameworks. To this end, we present CHO benchmark suite an extension of CHStone, a commonly used C-based high-level synthesis benchmark suite, for OpenCL. We characterise CHO at various levels and use it to investigate compiling non-trivial software to FPGAs. CHO is work in progress and more benchmarks will be added with time.

Keyword(s)

Accelerator; FPGA; High-Level Synthesis; OpenCL

Bibliographic metadata

Type of resource:

text

Content type:

Conference contribution

Conference contribution title:

CHO: Towards a Benchmark Suite for OpenCL FPGA Accelerators

Author(s) list:

Geoffrey Ndu, Javier Navaridas, Mikel Lujan

Conference title:

3rd IWOCL International Workshop on OpenCL

Conference venue:

Palo Alto, California, USA

Conference start date:

2015-05-11

Conference end date:

2015-05-13

Abstract:

Keyword(s):

Related website(s):

Source Code https://github.com/IT302/cho

Institutional metadata

University researcher(s):

Ndu, Geoffrey

Academic department(s):

Record metadata

Manchester eScholar ID:

uk-ac-man-scw:263819

Created by:

Ndu, Geoffrey

Created:

2nd May, 2015, 12:09:10

Last modified by:

Ndu, Geoffrey

Last modified:

2nd November, 2015, 13:55:03