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CHO: A Benchmark Suite for OpenCL-based FPGA Accelerators

Ndu, Geoffrey; Lujan, Mikel; Navaridas, Javier

Manchester, UK; 2014.

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Abstract

Programming FPGAs with OpenCL-based high-level synthesis frameworks is gaining attention with a number of commercial and research frameworks announced. However, there are no benchmarks for evaluating these frameworks. To this end, we present CHO benchmark suite an extension of CHStone, a commonly used C-based high-level synthesis benchmark suite, for OpenCl. We characterise CHO at various levels and use it to investigate compiling non-trivial software to FPGAs.

Keyword(s)

Accelerator; Altera; FPGA; High-level synthesis; OpenCL; Software

Bibliographic metadata

Type of resource:

text

Content type:

Technical report

Report title:

CHO: A Benchmark Suite for OpenCL-based FPGA Accelerators

Author(s):

Report series title:

University of Manchester Technical Report

Publication date:

2014-05

Place of publication:

Manchester, UK

Report number:

UNIMAN-COMP-APT-TR-02-05-2014

Total pages:

Abstract:

Keyword(s):

Related website(s):

Related website http://it302.github.io/cho/

Institutional metadata

University researcher(s):

Ndu, Geoffrey

Academic department(s):

Record metadata

Manchester eScholar ID:

uk-ac-man-scw:228247

Created by:

Ndu, Geoffrey

Created:

1st July, 2014, 19:58:11

Last modified by:

Ndu, Geoffrey

Last modified:

2nd November, 2015, 13:54:53